A Multihit Time-to-Digital Converter Architecture on FPGA | Semantic Scholar
Applied Sciences | Free Full-Text | High-Resolution Digital-to-Time Converter Implemented in an FPGA Chip | HTML
FPGA implementation of a high-resolution time-to-digital converter | Semantic Scholar
Applied Sciences | Free Full-Text | High-Resolution Digital-to-Time Converter Implemented in an FPGA Chip | HTML
A 6.6 ps RMS resolution time-to-digital converter using interleaved sampling method in a 28 nm FPGA: Review of Scientific Instruments: Vol 90, No 4
Figure 1 from A 3.9-ps RMS Precision Time-to-Digital Converter Using Ones-Counter Encoding Scheme in a Kintex-7 FPGA | Semantic Scholar
Time‐to‐digital converters—A comprehensive review - Mattada - 2021 - International Journal of Circuit Theory and Applications - Wiley Online Library
High-Resolution Time-to-Digital Converter in Field Programmable Gate Array
An FPGA-Integrated Time-to-Digital Converter Based on a Ring Oscillator for Programmable Delay Line Resolution Measurement
A high resolution time-to-digital-convertor based on a carry-chain and DSP48E1 adders in a 28-nm field-programmable-gate-array: Review of Scientific Instruments: Vol 91, No 2
Subnanosecond time-to-digital converter implemented in a Kintex-7 FPGA - ScienceDirect
Firmware-only implementation of Time-to-Digital Converter (TDC) in Field-Programmable Gate Array (FPGA) - UNT Digital Library
A flexible 32-channel time-to-digital converter implemented in a Xilinx Zynq-7000 field programmable gate array - ScienceDirect
FPGA designs for reconfigurable converters - Basic FPGA TDCs
Block diagram of the FPGA embedded Time-To-Digital converter. | Download Scientific Diagram